The semiconductor industry currently uses different types of semiconductor-based imagers, such as charge coupled devices (CCDs), photodiode arrays, charge injection devices and hybrid focal plane arrays, among others.
Because of the inherent limitations and expense of CCD technology, CMOS imagers have been increasingly used as low cost imaging devices. A CMOS imager circuit includes a focal plane array of pixel cells, each one of the cells including either a photodiode, a photogate or a photoconductor overlying a doped region of a substrate for accumulating photo-generated charge in the underlying portion of the substrate. A readout circuit is connected to each pixel cell and includes a charge transfer section formed on the substrate adjacent the photodiode, photogate or photoconductor having a sensing node, typically a floating diffusion node, connected to the gate of a source follower output transistor. The imager may include at least one transistor for transferring charge from the charge accumulation region of the substrate to the floating diffusion node and also has a transistor for resetting the diffusion node to a predetermined charge level prior to charge transference.
In a CMOS image sensor, the active elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) transfer of charge to the floating diffusion node accompanied by charge amplification; (4) resetting the floating diffusion node to a known state before the transfer of charge to it; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge from the floating diffusion node. Photo-generated charge may be amplified when it moves from the initial charge accumulation region to the floating diffusion node. The charge at the floating diffusion node is typically converted to a pixel output voltage by a source follower output transistor.
CMOS imaging circuits of the type discussed above are generally known and discussed in, for example, Nixon et al., “256.times.256 CMOS Active Pixel Sensor Camera-on-a-Chip,” IEEE Journal of Solid-State Circuits, Vol. 31(12), pp. 2046-2050 (1996); and Mendis et al., “CMOS Active Pixel Image Sensors,” IEEE Transactions on Electron Devices, Vol. 41(3), pp. 452-453 (1994), the disclosures of which are incorporated by reference herein.
A schematic top view of a semiconductor wafer fragment of an exemplary CMOS sensor pixel four-transistor (4T) cell 10 is illustrated in FIG. 1. As it will be described below, the CMOS sensor pixel cell 10 includes a photo-generated charge accumulating area 21 in an underlying portion of the substrate. This area 21 is formed as a pinned photodiode 11 (FIG. 2) formed as part of a p-n-p structure within a substrate 20. The pinned photodiode is termed “pinned” because the potential in the photodiode is pinned to a constant value when the photodiode is fully depleted. It should be understood, however, that the CMOS sensor pixel cell 10 may include a photogate or other image to charge converting device, in lieu of a pinned photodiode, as the initial accumulating area 21 for photo-generated charge.
The CMOS image sensor 10 of FIG. 1 has a transfer gate 30 for transferring photoelectric charges generated in the charge accumulating region 21 to a floating diffusion region (sensing node) 25. The floating diffusion region 25 is further connected to a gate 50 of a source follower transistor. The source follower transistor provides an output signal to a row select access transistor having gate 60 for selectively gating the output signal to terminal 32. A reset transistor having gate 40 resets the floating diffusion region 25 to a specified charge level before each charge transfer from the charge accumulating region 21.
A cross-sectional view of the exemplary CMOS image sensor 10 of FIG. 1 taken along line 2-2′ is illustrated in FIG. 2. The charge accumulating region 21 is formed as a pinned photodiode 11 which has a photosensitive or p-n-p junction region formed by a p-type layer 24, an n-type region 26 and the p-type substrate 20. The pinned photodiode 11 includes two p-type regions 20, 24 so that the n-type photodiode region 26 is fully depleted at a pinning voltage. Impurity doped source/drain regions 22 (FIG. 1), preferably having n-type conductivity, are provided on either side of the transistor gates 40, 50, 60. The floating diffusion region 25 adjacent the transfer gate 30 is also preferable n-type.
FIG. 2 also illustrates trench isolation regions 15 formed in the active layer 20 adjacent the charge accumulating region 21. The trench isolation regions 15 are typically formed using a conventional STI process or by using a Local Oxidation of Silicon (LOCOS) process. A translucent or transparent insulating layer 55 formed over the CMOS image sensor 10 is also illustrated in FIG. 2. Conventional processing methods are used to form, for example, contacts 32 (FIG. 1) in the insulating layer 55 to provide an electrical connection to the source/drain regions 22, the floating diffusion region 25, and other wiring to connect to gates and other connections in the CMOS image sensor 10.
Generally, in CMOS image sensors such as the CMOS image sensor cell 10 of FIGS. 1-2, incident light causes electrons to collect in region 26. A maximum output signal, which is produced by the source follower transistor having gate 50, is proportional to the number of electrons to be extracted from the region 26. The maximum output signal increases with increased electron capacitance or acceptability of the region 26 to acquire electrons. The electron capacity of pinned photodiodes typically depends on the doping level of the image sensor and the dopants implanted into the active layer.
Minimizing dark current in the photodiode is important in CMOS image sensor fabrication. Dark current is generally attributed to leakage in the charge collection region 21 of the pinned photodiode 11 and is strongly dependent on the doping implantation conditions of the CMOS image sensor. High dopant concentrations in electrical connection region 23 (FIG. 2) typically increase dark current. In addition, defects and trap sites inside or near the photodiode depletion region strongly influence the magnitude of dark current generated. Dark current is a result of current generated from trap sites inside or near the photodiode depletion region; band-to-band tunneling induced carrier generation as a result of high fields in the depletion region; junction leakage coming from the lateral sidewall of the photodiode; and leakage from isolation corners, for example, stress induced and trap assisted tunneling.
A common problem associated with the pinned photodiode 11 of FIG. 2 is the generation of dark current as a result of gate-induced drain leakage (GIDL) in transfer gate overlap region 27 (FIG. 2). The transfer gate overlap region 27 is under gate 30 and permits an electrical connection between the n-type photodiode depletion region 26 and the diffusion node 25 when the transfer gate is turned on. As a result of the transfer gate overlap region 27 (FIG. 2), an undesirable barrier potential might exist in this region which further affects the full transfer of charge from the photodiode 11 when it is filly depleted.
To reduce this barrier potential, different masks can be used for the formation of the n-type photodiode region 26 and of the subsequently formed p-type pinned surface layer 24. For example, after the formation of the n-type photodiode depletion region 26 with a first mask, a second mask is employed so that high doses of low energy p-type dopant are implanted to form the p-type pinned surface layer 24. The second mask is preferably offset from the edge of transfer gate 30 to reduce the undesirable barrier potential. At the same time, however, the second mask must also have a good overlap in the field oxide region 15 for a better hookup of the p-type pinned surface layer 24 to sidewall 16 of the field oxide region 15 and region 23. Thus, the second mask is of critical importance to the formation of the pinned layer and the reduction of the gate-induced drain leakage (GIDL), which further affects dark current, in transfer gate overlap region 27. Mask misalignment may occur as a result of using several masks and this, in turn, affects the physical and electrical properties of the pinned layer.
CMOS imagers also typically suffer from poor signal to noise ratios and poor dynamic range as a result of the inability to fully collect and store the electric charge collected in the region 26. Since the size of the pixel electrical signal is very small due to the collection of electrons in the region 26 produced by photons, the signal to noise ratio and dynamic range of the pixel should be as high as possible.
There is needed, therefore, an improved active pixel photosensor for use in a CMOS imager that exhibits reduced dark current and an offset region within the transfer gate overlap region of the pixel sensor cell formed without incurring problems of mask misalignment which might affect pixel performance. A method of fabricating an active pixel photosensor exhibiting these improvements is also needed.